diff --git a/VectoCore/Models/SimulationComponent/Impl/TimeBasedDrivingCycle.cs b/VectoCore/Models/SimulationComponent/Impl/TimeBasedDrivingCycle.cs index 1f561614b3a0e6fce5555036f80559fe3e3c200f..77f0de09fd09a4990832b4f38c22f964add5678e 100644 --- a/VectoCore/Models/SimulationComponent/Impl/TimeBasedDrivingCycle.cs +++ b/VectoCore/Models/SimulationComponent/Impl/TimeBasedDrivingCycle.cs @@ -29,12 +29,14 @@ namespace TUGraz.VectoCore.Models.SimulationComponent.Impl #region IDrivingCycle public bool DoSimulationStep() { - if (Data.Entries.Count >= CurrentStep) + if (CurrentStep >= Data.Entries.Count) return false; var entry = Data.Entries[CurrentStep]; - dt = TimeSpan.FromSeconds(entry.Time) - AbsTime; + //todo: variable time steps! + dt = TimeSpan.FromSeconds(1); + OutPort.Request(AbsTime, dt, entry.VehicleSpeed, entry.RoadGradient); AbsTime += dt; CurrentStep++; diff --git a/VectoCoreTest/Models/Simulation/DrivingCycleTests.cs b/VectoCoreTest/Models/Simulation/DrivingCycleTests.cs index 4bbc521bf7846a72c376ff312a05db60a97b92a1..1b37619d1f5c117f1336333df7ba3e32427b0589 100644 --- a/VectoCoreTest/Models/Simulation/DrivingCycleTests.cs +++ b/VectoCoreTest/Models/Simulation/DrivingCycleTests.cs @@ -1,4 +1,5 @@ -using Microsoft.VisualStudio.TestTools.UnitTesting; +using System; +using Microsoft.VisualStudio.TestTools.UnitTesting; using TUGraz.VectoCore.Models.Simulation.Impl; using TUGraz.VectoCore.Models.Connector.Ports; using TUGraz.VectoCore.Models.Simulation.Data; @@ -92,5 +93,37 @@ namespace TUGraz.VectoCore.Tests.Models.Simulation Assert.AreEqual(0.03, outPort.Gradient); Assert.AreEqual(0.5, dataWriter[ModalResultField.time]); } + + [TestMethod] + public void TestTimeBasedTimeFieldMissing() + { + var container = new VehicleContainer(); + + var cycleData = DrivingCycleData.ReadFromFileTimeBased(@"TestData\Cycles\Cycle time field missing.vdri"); + IDrivingCycle cycle = new TimeBasedDrivingCycle(container, cycleData); + + var outPort = new MockDriverDemandOutPort(); + + var inPort = cycle.InPort(); + + inPort.Connect(outPort); + + var dataWriter = new TestModalDataWriter(); + var absTime = new TimeSpan(); + var dt = TimeSpan.FromSeconds(1); + var time = 0.5; + + while (cycle.DoSimulationStep()) + { + container.CommitSimulationStep(dataWriter); + + Assert.AreEqual(absTime, outPort.AbsTime); + Assert.AreEqual(dt, outPort.Dt); + Assert.AreEqual(time, dataWriter[ModalResultField.time]); + + time = time + dt.TotalSeconds; + absTime += dt; + } + } } } diff --git a/VectoCoreTest/TestData/Cycles/Cycle time field missing.vdri b/VectoCoreTest/TestData/Cycles/Cycle time field missing.vdri new file mode 100644 index 0000000000000000000000000000000000000000..83052339fe6c96e1210a22b1d0bb0b5dc797dbec --- /dev/null +++ b/VectoCoreTest/TestData/Cycles/Cycle time field missing.vdri @@ -0,0 +1,14 @@ +<v>,<grad>,<Padd>,<Aux_ALT1>,<Aux_ALT2>,<Aux_ALT3> +0,-0.020237973,6.1,0.25,0.25,0.25 +64,-0.020237973,6.1,0.25,0.25,0.25 +64,-0.020237973,6.1,0.25,0.25,0.25 +64,-0.020237973,6.1,0.25,0.25,0.25 +64,-0.020237973,6.1,0.25,0.25,0.25 +64,-0.020237973,6.1,0.25,0.25,0.25 +64,-0.020237973,6.1,0.25,0.25,0.25 +64,-0.020237973,6.1,0.25,0.25,0.25 +64,-0.020237973,6.1,0.25,0.25,0.25 +64,-0.020237973,6.1,0.25,0.25,0.25 +64,-0.020237973,6.1,0.25,0.25,0.25 +64,-0.020237973,6.1,0.25,0.25,0.25 +64,-0.020237973,6.1,0.25,0.25,0.25 \ No newline at end of file diff --git a/VectoCoreTest/VectoCoreTest.csproj b/VectoCoreTest/VectoCoreTest.csproj index 8d37423ed130625ad7d4fca843e0cfa78a381c63..8e9c0af4d17c34da9d070e014c5cb5c4f26f9aa1 100644 --- a/VectoCoreTest/VectoCoreTest.csproj +++ b/VectoCoreTest/VectoCoreTest.csproj @@ -109,6 +109,9 @@ <None Include="TestData\Components\FullLoadCurve insufficient entries.vfld"> <CopyToOutputDirectory>PreserveNewest</CopyToOutputDirectory> </None> + <None Include="TestData\Cycles\Cycle time field missing.vdri"> + <CopyToOutputDirectory>PreserveNewest</CopyToOutputDirectory> + </None> <None Include="TestData\Cycles\Coach.vdri"> <CopyToOutputDirectory>PreserveNewest</CopyToOutputDirectory> </None>